This invention generally relates to analog to digital converters (ADC), and more specifically to control of an ADC.
Analog to digital converters are well known and are commonly used to convert an analog signal into a digital representation by periodically sampling the analog signal to form a sequence of digital values. A simple ADC generally provides a low resolution digital representation for each sample, such as an eight-bit value, for example. More complex ADCs provide higher accuracy""s, such a sixteen-bit values, or higher. ADCs are often included within a digital system that includes a microprocessor or a micro controller as part of a compliment of peripheral devices. Operation of the ADC may be controlled by software executed on the associated microprocessor.
Microprocessors are general purpose processors which provide high instruction throughputs in order to execute software running thereon, and can have a wide range of processing requirements depending on the particular software applications involved. Many different types of processors are known, of which microprocessors are but one example. For example, Digital Signal Processors (DSPs) are widely used, in particular for specific applications, such as mobile processing applications and for embedded controllers. DSPs are typically configured to optimize the performance of the applications concerned and to achieve this they employ more specialized execution units and instruction sets. Particularly in applications such as mobile telecommunications, but not exclusively, it is desirable to provide ever increasing DSP performance while keeping power consumption as low as possible.
In general, and in a form of the present invention a digital system is provided with an analog to digital converter (ADC) with input multiplexor circuitry having a set of analog input terminals for receiving a plurality of analog signals. The input multiplexor is responsive to a select input. A sequence state machine is controllably connected to the input multiplexor select input, and has number of programmable states. The state machine is operable to auto-sequence a series of conversions by the ADC. Each of the programmable states can be programmed to select any one of the set of analog input terminals. A set of result registers is connected to an output of the ADC, and each result register operable to receive a conversion result from the ADC corresponding to a respective state of the sequence state machine.
According to another aspect of the present invention, a second sequence state machine is controllably connected to the input multiplexor select input and also has a number of programmable states. The second sequence state machine is also operable to auto-sequence a series of conversions by the ADC and to select any one of the set of analog input terminals. Arbitration circuitry is connected to the first sequence state machine and to the second sequence state machine and is operable to enable either the first sequence state machine or the second sequence state machine to control the ADC.
According to another aspect of the present invention, mode control circuitry is connected to the first sequence state machine and to the second sequence state machine and is operable to select a cascade mode of operation, wherein the second sequence state machine is enabled to operate in a cascade manner with the first sequence state machine.